(1) Field of the Invention
The present invention relates to semiconductor manufacturing processing, and more particularly to a chemical/mechanical polishing (CMP) process for making tungsten metal plugs in low-k (having a low dielectric constant) intermetal dielectric (IMD) layers. The method uses a hard mask and a two-step selective CMP process for making tungsten plugs that are planar with the low-k IMD layer and avoids polishing damage such as erosion and dishing of the IMD layer.
(2) Description of the Prior Art
The packing density of devices on integrated circuits has dramatically increased on ultra-large scale integrated (ULSI) circuits due to advances in semiconductor processing, such as the use of high-resolution photolithography and anisotropic plasma etching. In this sub-micron technology the allowed packing density of devices on an integrated circuit is strongly dependent on the metal interconnection density. As future design rules are more aggressively scaled down, for example, down to 0.18 to 0.1 micrometers (um), more levels of metal are required to effectively interconnect the high density of discrete devices on the chip.
However, as the number of metal levels increases and the topography gets rougher, it becomes increasingly difficult to pattern the metal levels. This results because a shallow depth of focus (DOF) is required when exposing the photoresist, and the rough topography can result in distorted photoresist images. Another problem is that it is difficult to etch sub-micron feature sizes in the metal layers using anisotropic etching without leaving residue in the underlying rough topography that can cause intralevel electrical shorts.
One method of circumventing these problems is to provide a planar surface and to use a damascene process in which contact openings and trench recesses are etched in the insulator. Then a metal is deposited and chem/mech polished back to provide metal plugs in the contact openings and metal interconnections in the recesses. This results in a planar surface for the next level of processing.
To improve the circuit performance by reducing the RC time constant, it is becoming increasing popular to use a low-k (low dielectric) insulator such as low-k polymers which make it difficult to chem/mech polish the overlying metal layers without damaging the polymer. It is also difficult to pattern the low-k polymer using a photoresist mask and oxygen (O.sub.2) plasma etching because of the poor etch selectivity between the photoresist and the polymer. Therefore a hard mask, such as silicon oxide (SiO.sub.2) or silicon nitride (Si.sub.3 N.sub.4), is used over the low-k polymer to provide a mask for selective etching. However, when the photoresist and hard mask are used to etch closely spaced contact openings in the low-k polymer, a severe erosion of the photoresist mask leads to a damaged oxide hard mask at the perimeter of the contact openings, which significantly degrades the planarity of the intermetal dielectric (IMD) layer (low-k polymer and hard mask). Then when the metal is deposited and polished back to form metal plugs in the contact openings, residual metal can result between adjacent metal plugs causing intralevel shorts.
Several methods of making these metal plugs in an insulating layer are described in the literature. Yu et al. in U.S. Pat. No. 5,244,534 teach a two-step chem/mech polishing method for making tungsten plugs in an insulating layer such as BPSG oxide. A first polishing step polishes a tungsten metal selectively to an oxide that results in recessed metal plugs in contact openings in the BPSG oxide. A second polishing step polishes the oxide selectively to the tungsten to remove any residual metal and to form an upward-protruding metal plug to provide a better contact for the next level of metal interconnections. Yu et al. do not address forming tungsten plugs in a low-k polymer layer. In Farkas et al., U.S. Pat. No. 5,614,444, a method is described for including an additive to a polishing slurry to increase the selectivity of the metal polishing to the underlying SiO.sub.2 layer. Huang et al. in U.S. Pat. No. 5,747,382 teach a method using a chem/mech polish to provide a planar surface, and a second reactive ion etching is used to remove contaminants in seams in the planarized layer that could cause eruptions during subsequent processing. Stager et al. in U.S. Pat. No. 5,707,492 describe a method of applying titanium to a polishing pad that provides a high polishing rate and good polishing uniformity in a polishing process. Jaso in U.S. Pat. No. 5,726,099 describes a method for using a touch-up slurry during chem/mech polishing that polishes the tungsten stud material and the insulating material (SiO.sub.2) at a nearly identical removal rate. Gambino et al. in U.S. Pat. No. 5,573,633 teach a method for forming metal plugs in via holes in a planar insulating layer using a thick polysilicon layer as a chem/mech polish stop layer. A short chem/mech polish is then used to remove the polysilicon. Joshi et al. in U.S. Pat. No. 5,403,779 describe a method for forming low resistance (AlCu or Cu) contact plugs having a refractory metal cap. The refractory metal cap protects the plugs while the AlCu or Cu is selectively removed on the remaining wafer surface. The structure is then made planar by chem/mech polishing or by selective reactive ion etching the refractory metal cap.
There is still a need in the semiconductor industry to provide an improved chem/mech polishing process that forms tungsten plugs in a low-k polymer insulating layer without dishing and corrosion of the surface of the low-k layer, while avoiding intralevel shorts between closely spaced tungsten plugs in via holes.